There is a current interest in CMOS active pixel imagers for use as low cost imaging devices. An exemplary pixel circuit of a CMOS active pixel sensor (APS) is described below with reference to FIG. 1, where the circuit is identified generally by reference number 100. Active pixel sensors can have one or more active transistors within the pixel unit cell, can be made compatible with CMOS technologies, and promise higher readout rates compared to passive pixel sensors. The pixel cell shown in FIG. 1 is a 3T APS pixel cell, identified by reference number 150, where the 3T is commonly used in the art to designate the use of three transistors to operate the pixel. A 3T APS includes has a photodiode 162, a reset transistor 184, a source follower transistor 186, and a row select transistor 188. It should be understood that while FIG. 1 shows the circuitry for operation of a single pixel, in practice the imager will be formed of an M times N array of identical pixels arranged in rows and columns, with the pixels of the array accessed using row and column select circuitry, as described in more detail below.
The photodiode 162 converts incident photons to electrons which collect at node A. A source follower transistor 186 has its gate connected to node A and thus amplifies the signal appearing at Node A. When a particular row containing cell 150 is selected by a row selection transistor 188, the signal amplified by transistor 186 is passed on a column line 170 to the readout circuitry. The photodiode 162 accumulates a photo-generated charge in a doped region of the substrate. It should be understood that the CMOS imager might include a photogate or other photo conversion device, in lieu of a photodiode, for producing photo-generated charge.
A reset voltage source Vrst is selectively coupled through reset transistor 184 to node A. The gate of reset transistor 184 is coupled to a reset control line 191 which serves to control the reset operation, i.e., the connection of Vrst to node A. Vrst may be equal to Vdd. The row select control line 160 is coupled to all of the pixels of the same row of the array. Voltage source Vdd is coupled to a source following transistor 186 and its output is selectively coupled to a column line 170 through row select transistor 188. Although not shown in FIG. 1, column line 170 is coupled to all of the pixels of the same column of the array and typically has a current sink at its lower end. The gate of row select transistor 188 is coupled to row select control line 160.
As known in the art, a value is read from pixel 150 in a two step process. During a charge integration period, the photodiode 162 converts photons to electrons which collect at the node A. The charge at node A is amplified by source follower transistor 186 and selectively passed to column line 170 by row access transistor 188. During a reset period, node A is reset by turning on reset transistor 184 to apply the reset voltage Vrst to node A, and this voltage is then read out to column line 170 by the source follower transistor 186 through the activated row select transistor 188. As a result, the two different values—the reset voltage Vrst and the image signal voltage Vsig—are readout from the pixel and sent by the column line 170 to the readout circuitry where each is sampled and held for further processing as known in the art.
All pixels in a row are read out simultaneously onto respective column lines 170 and the column lines are activated in sequence for reset and signal voltage read out. The rows of pixels are also read out in sequence onto the respective column lines.
FIG. 2 shows a CMOS active pixel sensor integrated circuit chip that includes an array of pixels 230 and a controller 232 which provides timing and control signals to control reading out of signals stored in the pixels in a manner commonly known to those skilled in the art. Exemplary arrays have dimensions of M times N pixels, with the size of the array 230 depending on a particular application. The imager is read out a row at a time using a column parallel readout architecture. The controller 232 selects a particular row of pixels in the array 230 by controlling the operation of row addressing circuit 234 and row drivers 240. Charge signals stored in the selected row of pixels are provided on the column lines 170 (FIG. 1) to a readout circuit 242 in the manner described above. The pixel signal read from each of the columns then can be read out sequentially using a column addressing circuit 244. Differential pixel signals (Vrst, Vsig) corresponding to the read out reset signal and integrated charge signal are provided as respective outputs Vout1, Vout2 of the readout circuit 242.
FIG. 3 more clearly shows the rows 321 and columns 349 of pixels 350. Each column includes multiple rows of pixels 350. Signals from the pixels 350 in a particular column can be read out to a readout circuit 351 associated with that column. The read out circuit 351 includes sample and hold circuitry for storing the pixel reset (Vrst) and integrated charge signals (Vsig). Signals stored in the readout circuits 351 then can be read sequentially column-by-column to an output stage 354 which is common to the entire array of pixels 330. The analog output signals can then be sent, for example, to a differential analog circuit and which subtracts the reset and integrated charge signals and sends them to an analog-to-digital converter (ADC), or the reset and integrated charge signals can be supplied directly to the analog-to-digital converter.
FIG. 4 more clearly shows the column readout circuit 351 that includes a sample and hold read out circuit 401 and an amplifier 434. The FIG. 4 circuit is capable of sampling and holding and then amplifying the Vsig and Vrst values for subsequent use by an output stage 354 (FIG. 3).
During manufacture, each imaging pixel array is usually tested individually. Tests detect defective pixel circuits, pixel signal level, and other array attributes, and the information is stored based on lot and individual device identification numbers. The information developed during testing can be utilized to enhance the operation of the device by, for example, compensating for defective pixels, differing pixel signal levels, and other tested pixel attributes.
Additionally, imaging sensors are not identifiable when they are being manufactured. The security/identification values are assigned after the complete system is manufactured, resulting in an additional step in manufacturing that also adds to the cost of manufacture. There is also an administrative burden with regard to keeping track of defective pixel information before an identification number is assigned, as the sensor and the defective pixel information related to the pixel must be physically tracked throughout the manufacturing process. If a sensor is misplaced in the manufacturing sequence, then the integrated circuit imaging array, and all the other integrated circuit imaging array that are mis-sequenced, must be re-tested.
A certain number of defective pixels per sensor is tolerated so that a given amount of sensors are deemed usable and manufacturing costs are recovered. In these sensors, pixels that are found to be defective do not exceed a predetermined number for the entire sensor nor do they exceed a predetermined number within a predetermined area. Although the locations of these pixels are discovered during testing, it is an administrative burden, as described above, to keep track of this information during manufacture. More importantly, ensuring that information about defective pixels are supplied with each sensor after manufacture adds to the cost of sensor production. For example, the company that manufactures the sensor must provide the company that manufactures the camera with defective pixel information. Most often, the defective pixel information is provided a separate media (e.g., a floppy disc, a computer-readable tape, or other computer-readable storage media), which adds to costs. And again, problems arise with matching each sensor with its defective pixel information.
CMOS imagers with on-chip programmable memory for storing pixel and identification information for a CMOS sensor array are known. For example, U.S. Pat. No. 6,396,539 (Heller et al.) discloses an on-chip programmable flash memory, which is complex and bulky. Using a programmable memory requires additional storage circuitry (i.e., the memory) and associated circuitry to read, write, and decipher the information in the memory. It would be desirable to provide an image sensor having on-chip storage system that minimizes the amount of additional circuitry needed to implement the memory. Additionally, it would be desirable to have an on chip storage system that does not require additional circuitry to access and interpret the stored information. A simple and easy way to store pixel array information on-chip for later use would also be desirable.